A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist

Author

Doris, Kostas ; Janssen, Erwin ; Nani, Claudio ; Zanikopoulos, Athon ; van der Weide, Gerard

Author_Institution

NXP Semicond., Eindhoven, Netherlands

fYear

2011

fDate

20-24 Feb. 2011

Firstpage

180

Lastpage

182

Abstract

Trends in cable TV reception for data and video require simultaneous capture of many channels, e.g., 16, arbitrary located in the 48-to-1002MHz TV band. The challenges of integrating more than two zero-IF tuners on a single die could be simplified with a low-power 10b ADC that can digitize the entire TV band and be suitable for integration with baseband DSP. This work presents a 64χ inter leaved 2.6GS/S 10b 65nm CMOS ADC with on-chip calibrations, combining interleaving hierarchy with an open-loop buffer array operated in feedforward sampling and feedback-SAR mode. The ADC achieves an SNDR of 48.5dB at Nyquist and consumes only 0.48W.

Keywords

CMOS integrated circuits; analogue-digital conversion; feedback; CMOS time-interleaved ADC; Nyquist; baseband DSP; bit rate 2.6 Gbit/s; cable TV reception; feedback-SAR mode; feedforward sampling; interleaving hierarchy; on-chip calibration; open-loop buffer array; power 480 mW; size 65 nm; Arrays; Bandwidth; CMOS integrated circuits; Calibration; Clocks; Linearity; Noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-61284-303-2

Type

conf

DOI

10.1109/ISSCC.2011.5746272

Filename

5746272