DocumentCode
2894111
Title
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
Author
Sheu, Shyh-Shyuan ; Chang, Meng-Fan ; Lin, Ku-Feng ; Wu, Che-Wei ; Chen, Yu-Sheng ; Chiu, Pi-Feng ; Kuo, Chia-Chen ; Yang, Yih-Shan ; Chiang, Pei-Chia ; Lin, Wen-Pin ; Lin, Che-He ; Lee, Heng-Yuan ; Gu, Pei-Yi ; Wang, Sum-Min ; Chen, Frederick T. ; Su, Ke
Author_Institution
ITRI, Hsinchu, Taiwan
fYear
2011
fDate
20-24 Feb. 2011
Firstpage
200
Lastpage
202
Abstract
This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random access time is presented. Multi-level-cell (MLC) operation with 160ns write-verify operation is demonstrated.
Keywords
embedded systems; random-access storage; MLC-access capability; embedded RRAM; embedded SLC resistive-RAM macro; read-write random-access time; single-level-cell RRAM macro; Delay; Electrical resistance measurement; Nonvolatile memory; Phase change random access memory; Resistance; Sensors; Solid state circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-61284-303-2
Type
conf
DOI
10.1109/ISSCC.2011.5746281
Filename
5746281
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