A hardware architecture for a parallel genetic algorithm for image registration

Real-time image analysis is one of the areas of research which would particularly benefit from parallel genetic algorithms (PGA); however, such algorithms are generally simulated on conventional computers or are designed for expensive hardware systems. For practical image processing on a large scale, cheap, fast and efficient PGA processors are required. Vision systems require processing techniques which are robust, fast and capable of dealing with large quantities of data. Genetic algorithms have been used because of the first of these criteria. However by using hardware parallel genetic algorithms the second and third criteria could also be fulfilled. Fitzpatrick suggests (1984) that a parallel implementation would be beneficial and various forms of PGA have been suggested by other authors. The nature of PGAs is described followed by the application of genetic algorithms to vision systems. A description of a hardware architecture for vision systems is detailed along with various modifications to improve the implementation. A simulation is used to produce results that verify the effectiveness of the hardware architecture and finally conclusions and future work are discussed