DocumentCode
289493
Title
Modelling in VHDL-A
Author
Zwolinski, M. ; Kazmierski, T.J.
Author_Institution
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
fYear
1994
fDate
1994
Firstpage
42430
Lastpage
42433
Abstract
VHDL (IEEE Standard 1076) is currently being extended to include mixed-signal and analogue modelling (VHDL-A). A draft standard is expected in 1995. This paper describes two models developed in VHDL-A. One of the design objectives of VHDL-A is compatibility with SPICE, and, therefore, a version of the SPICE Level 3 MOS model has been written. The second model is of a phase-locked loop, including a VCO. As the standard is not complete, no VHDL-A simulators are available to verify these models. Nevertheless, it has been possible to investigate several important aspects of modelling with VHDL-A
Keywords
SPICE; circuit analysis computing; hardware description languages; integrated circuit modelling; EEE Standard 1076; SPICE; SPICE Level 3 MOS model; VCO; VHDL-A; modelling; phase-locked loop;
fLanguage
English
Publisher
iet
Conference_Titel
Mixed Mode Modelling and Simulation, IEE Colloquium on
Conference_Location
London
Type
conf
Filename
383646
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