DocumentCode
2895987
Title
Polymorphic wavelet architectures using reconfigurable hardware
Author
Pande, Amit ; Zambreno, Joseph
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA
fYear
2008
fDate
8-10 Sept. 2008
Firstpage
471
Lastpage
474
Abstract
Traditional microprocessor-based solutions are insufficient to serve the dynamic throughput demands of real-time scalable multimedia processing systems. This paper introduces a Polymorphic Architecture for the Discrete Wavelet Transform (Poly-DWT) as a building block of reconfigurable systems to address these needs. We illustrate how our Poly-DWT architecture can dynamically make resource allocation decisions according to application requirements. We perform a quantitative analysis of our Poly-DWT architecture using an FPGA prototype, and compare our filters to existing approaches to illustrate the area and performance benefits inherent in our approachrdquo.
Keywords
field programmable gate arrays; logic design; reconfigurable architectures; wavelet transforms; FPGA; discrete wavelet transform; microprocessor-based solutions; polymorphic wavelet architectures; quantitative analysis; real-time scalable multimedia processing systems; reconfigurable hardware; resource allocation; Discrete wavelet transforms; Field programmable gate arrays; Filters; Hardware; Multimedia systems; Performance analysis; Prototypes; Real time systems; Resource management; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location
Heidelberg
Print_ISBN
978-1-4244-1960-9
Electronic_ISBN
978-1-4244-1961-6
Type
conf
DOI
10.1109/FPL.2008.4629986
Filename
4629986
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