A New CMOS 3.1-11.7 GHz Low Power LNA for Ultra-Wideband Wireless Applications

Author

Reja, Md Mahbub ; Sellathamby, C. ; Filanovsky, Igor

Author_Institution

Scanimetrics, Inc., Edmonton, Alta.

fYear

2007

fDate

27-30 May 2007

Firstpage

1453

Lastpage

1456

Abstract

In this paper, a new 3.1 GHz to 11.7 GHz ultra-wide-band (UWB) low-noise amplifier (LNA) is designed in 0.18-mum RF CMOS process. The proposed circuit includes a common-source cascode amplifier followed by an output buffer stage. Special attention is paid to design of inter-stage circuit employing the combined shunt and double-series inductive peaking bandwidth enhancement technique. The amplifier exhibits a forward gain (S21) of 11.0-11.5 dB, a noise figure (NF) of 3.6-4.4 dB, and input return loss (S11) of less than -9.3 dB over the frequency range of 3.1 GHz to 11.7 GHz while consuming only 6.2 mW from a power supply of 1.5 V.

Keywords

CMOS analogue integrated circuits; integrated circuit design; low noise amplifiers; low-power electronics; microwave amplifiers; radiocommunication; ultra wideband communication; 0.18 micron; 1.5 V; 11.0 to 11.5 dB; 3.1 to 11.7 GHz; 3.6 to 4.4 dB; 6.2 mW; RF CMOS process; common-source cascode amplifier; double-series inductive peaking bandwidth enhancement technique; inter-stage circuit design; low power LNA; shunt inductive peaking bandwidth enhancement technique; ultra wideband low-noise amplifier; ultra-wideband wireless applications; Bandwidth; CMOS process; Circuits; Low-noise amplifiers; Noise figure; Noise measurement; Power amplifiers; Radio frequency; Radiofrequency amplifiers; Ultra wideband technology; Ultra-wideband; inter-stage design; low-noise amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378576

Filename

4252923