Developments in `smart´ custom image sensors at the University of Brighton

Any image processing that can be performed within the sensor itself has the potential to dramatically reduce the communication and processing workload of the host controller. Thus onchip processing has an important role to play in the viability of visual servoing applications. When coupled with the increasing accessibility of custom VLSI design this makes the development of ´smart´ image sensing architectures attractive. Investigations into a proprietary optic DRAM image sensor suggested a sensing mechanism based upon selective sensitisation of photosites that would allow edge-detection of binary images to be performed in the focal plane of the sensor. This mechanism was chosen as the vehicle for development of a prototype ´smart´ custom VLSI image sensor. A 32x32 array featuring this unique unit cell architecture was implemented in a 2 micron ES2 CMOS process. Each unit cell was 80.5 microns square and featured a diode photosite which occupied 24% of the total area, the remainder being concerned with buffering, binarisation and edge-extraction hardware. The requirement for support circuitry was met by a rack containing three Eurocards with a microprocessor