• DocumentCode
    2898890
  • Title

    Tombstone reduction by reflow profile optimization, SMT stencil design and pad design

  • Author

    Ming, Ho Tuck ; Ming, Tan Kong ; Khor, Lily

  • Author_Institution
    Carsem Technol. Center, Carsem (M) Sdn Bhd S-Site, Ipoh, Malaysia
  • fYear
    2010
  • fDate
    Nov. 30 2010-Dec. 2 2010
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    With the technology advancing, most products are getting more personalize with various variety. Hand held products that are larger than palm size has no longer favor one´s interest; the miniature product is the future, its means smaller, lighter and portable. Miniaturization product can be succeeded by reducing package size and the integration of ultra-small component (0402, 0201, 01005). SIP-MCM (system in package-multichip module) is one of the technologies that involve; this package is built with the combination of multiple dies and miniature passive components in SMT processes. In SMT process, small chip components prone to have tombstone defect Tombstone defect is defined when one of the component terminal stay intact whereas the other lifted up (Figure 1). The phenomenon occurred was mainly due to imbalance wetting force during reflow. Small component like 0402/0201 is rather light and delicate; the movement can be easily influenced by the surface tension between pad and molten solder. Imagine a small 0201 component has to balance the imbalance pulling force on its left and right terminals. On bigger component sizes from 1206 onwards, tombstoning is not often seen because of its weight factor. This paper is to discuss the understanding of tombstone problem in SIP-MCM and the study of 0402/0201 component tombstone reduction methods which were evaluated on reflow profile, substrate design and stencil opening.
  • Keywords
    integrated circuit design; multichip modules; reflow soldering; surface mount technology; system-in-package; SIP-MCM; SMT; Tombstone defect; imbalance pulling force; imbalance wetting force; pad design; reflow profile optimization; stencil design; system in package-multichip module; Assembly; Capacitors; Inspection; Packaging; Radiation detectors; Resistors; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International
  • Conference_Location
    Melaka
  • ISSN
    1089-8190
  • Print_ISBN
    978-1-4244-8825-4
  • Type

    conf

  • DOI
    10.1109/IEMT.2010.5746716
  • Filename
    5746716