DocumentCode
2901429
Title
BiCMOS submicron compiler memories
Author
Drummond, John ; Lepkowski, Marlene
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
An advanced submicron BiCMOS process and an ASIC memory compiler are discussed. The BICMOS process uses bipolar transistors to enhance the fast CMOS transistors by driving heavily loaded nodes at high speeds. The multiple layers of metal in the process significantly increase the gate density available for system-level design
Keywords
BIMOS integrated circuits; SRAM chips; VLSI; application specific integrated circuits; read-only storage; ASIC memories; ASIC memory compiler; BiCMOS submicron compiler memories; bipolar transistors; gate density; multilayer metal; submicron BiCMOS process; system-level design; Application specific integrated circuits; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; Instruments; Integrated circuit interconnections; Libraries; Random access memory; Read only memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186106
Filename
186106
Link To Document