An 8×8 discrete cosine transform chip with pixel rate clocks

Author

D´Luna, L.J. ; Cook, W.A. ; Guidash, R.M. ; Brown, G.W. ; Tredwell, T.J. ; Fischer, J.R. ; Tarn, T.

Author_Institution

Eastman Kodak Co., Rochester, NY, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

Image compression is an established means of meeting storage and transmission requirements for image data. One method is transform domain compression using the two-dimensional discrete cosine transform (DCT) on 8×8 image blocks. A 2-μm CMOS chip that computes this transform in real-time using clocks that are no faster than the pixel rate is described. The architecture uses a distributed arithmetic processing scheme to compute two one-dimensional transforms interposed with an unconventional matrix transpose RAM. The design methodology that includes layout, simulation, verification and test, using a silicon compiler tool-set, is described

Keywords

CMOS integrated circuits; application specific integrated circuits; circuit layout CAD; computerised picture processing; data compression; transforms; 2 micron; 2D DCT; 2D discrete cosine transform; 8×8 image blocks; CMOS chip; design methodology; distributed arithmetic processing scheme; image compression; layout; matrix transpose RAM; pixel rate clocks; real time computation; silicon compiler tool-set; simulation; test; transform domain compression; verification; Arithmetic; Clocks; Computational modeling; Computer architecture; Design methodology; Discrete cosine transforms; Discrete transforms; Distributed computing; Image coding; Image storage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186139

Filename

186139