DocumentCode
2902290
Title
Design of Very Low Noise 4.2GHz Clapp VCOs
Author
Jonnalagedda, Raghuram ; Mayaram, Kartikeya
Author_Institution
RF/Analog IC Design, Qualcomm Inc., San Diego, CA
fYear
2007
fDate
27-30 May 2007
Firstpage
2862
Lastpage
2865
Abstract
A fully integrated 4.2GHz single-ended clapp VCO is presented in 0.25mum CMOS technology. The PMOS-based VCO is voltage biased using an inductor to achieve higher swing and better phase noise. With an inductor Q of only 6.5, the VCO achieves a phase noise of -143.5dBc/Hz at 3MHz offset, resulting in a figure of merit of -188.9dBc/Hz.
Keywords
CMOS integrated circuits; integrated circuit design; microwave integrated circuits; microwave oscillators; 0.25 micron; 3 MHz; 4.2 GHz; CMOS technology; PMOS-based VCO; figure of merit; inductor; integrated clapp VCO design; phase noise; voltage controlled oscillators; CMOS technology; Circuit topology; Inductors; Integrated circuit noise; Phase noise; Pulse amplifiers; Steady-state; Transceivers; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378769
Filename
4253275
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