DocumentCode
2903658
Title
Compact model and performance estimation for tunneling nanowire FET
Author
Solomon, P.M. ; Frank, D.J. ; Koswatta, S.O.
Author_Institution
T.J. Watson Res. Center, IBM, Yorktown Heights, VA, USA
fYear
2011
fDate
20-22 June 2011
Firstpage
197
Lastpage
198
Abstract
A compact model is presented which realistically reproduces TFET characteristics and allows complex circuit simulation and parameter optimization studies. The model has been applied to circuit simulations which reveal anomalous switching behavior, and to a multi-parameter optimization study which quantifies the power-performance advantage of the TFET over conventional MOSFETs.
Keywords
field effect transistors; nanowires; tunnelling; TFET; circuit simulation; compact model; multiparameter optimization; performance estimation; tunneling nanowire FET; Capacitance; Clocks; Delay; Integrated circuit modeling; Logic gates; Switches; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Device Research Conference (DRC), 2011 69th Annual
Conference_Location
Santa Barbara, CA
ISSN
1548-3770
Print_ISBN
978-1-61284-243-1
Electronic_ISBN
1548-3770
Type
conf
DOI
10.1109/DRC.2011.5994495
Filename
5994495
Link To Document