At-Speed Testing with Timing Exceptions and Constraints-Case Studies

Author

Goswami, Dhiraj ; Tsai, Kun-Han ; Kassab, Mark ; Kobayashi, Takeo ; Rajski, Janusz ; Swanson, Bruce ; Walters, Darryl ; Sato, Yasuo ; Asaka, Toshiharu ; Aikyo, Takashi

Author_Institution

Mentor Graphics Corp., Wilsonville, OR

fYear

2006

fDate

Nov. 2006

Firstpage

153

Lastpage

162

Abstract

In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism

Keywords

automatic test pattern generation; integrated circuit testing; logic testing; timing; at-speed testing; correct-by-construction at-speed patterns; timing constraints; timing exceptions; Circuit testing; Clocks; Constraint optimization; Data mining; Design optimization; Graphics; Logic testing; Semiconductor device testing; Test pattern generators; Timing; At-speed test; Synopsys Design Constraints (SDC); false paths; multicycle paths.; static timing analysis (STA); timing constraints; timing exceptions;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2006. ATS '06. 15th Asian

Conference_Location

Fukuoka

ISSN

1081-7735

Print_ISBN

0-7695-2628-4

Type

conf

DOI

10.1109/ATS.2006.261014

Filename

4030762