CMOS High Power SPDT Switch using Multigate Structure

A novel CMOS high power RF switch using the multi-gate structure in a 0.18-mum triple-well CMOS process is designed, implemented, and characterized. The receive switch incorporates the multi-gate structure in order to provide high power handling capability to the transmit switch side. In addition, the RF switch with the multi-gate structure reduces insertion loss more than the one with the stacked transistor by reducing parasitic capacitance to the substrate. For performance comparison purposes, a triple-gate, and dual-gate NMOS switch were fabricated and characterized. Experimental data show that the SPDT switch exhibits 26 dBm of P1dB with the triple gate structure, and 24 dBm of P1dB with the dual gate structure at 900 MHz and 1.9 GHz. The multi-gate switch demonstrates 0.2 dB lower insertion loss than the multi-stacked switch. The switch die is also minimized by employing the compact multi-gate layout structure. Compared to the multi-stacked structure using an RF NMOS device in standard CMOS process, the die size of the triple gate and the dual gate is reduced by 50 % in both cases.