Parallel error-trapping and error-detection decoding

Author

Lee, Patrick ; Chang, Stanley

Author_Institution

Western Digital Corp., San Jose, CA, USA

fYear

1991

fDate

4-6 Nov 1991

Firstpage

35

Abstract

The authors present a parallel decoding method for a concatenated outer (nearest the channel) error-correcting code (ECC) and inner (nearest the user) error-detecting code (EDC). This method can be used if (1) both the ECC and EDC are linear codes, (2) the ECC decoder can be implemented as an error-trapping decoder, and (3) the EDC decoder is realized by a polynomial division circuit. The parallel decoding algorithm is described when the received codeword is corrected by both a forward and a backward error-trapping ECC decoder. A mathematical justification for the algorithm is presented

Keywords

error correction codes; error detection codes; backward error-trapping; concatenated outer ECC; error-detection decoding; error-trapping decoder; forward error-trapping; inner EDC; linear codes; parallel decoding; polynomial division circuit; received codeword; Circuit noise; Concatenated codes; Decoding; Delay effects; Error correction; Error correction codes; Galois fields; Hardware; Linear code; Polynomials;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-2470-1

Type

conf

DOI

10.1109/ACSSC.1991.186409

Filename

186409