A scalable orthogonal multiprocessor architecture

Author

Tung, Cheng-Hsien

Author_Institution

Dept. of Comput. Sci. & Eng., Connecticut Univ., Storrs, CT, USA

fYear

1991

fDate

4-6 Nov 1991

Firstpage

59

Abstract

The author proposes a multiple bus architecture capable of supporting a large number of processors to handle large amounts of data. This architecture has an orthogonal bus structure which maximizes bus bandwidth while reducing contention and arbitration overhead. Each processor is fully connected to memory through isolated buses. It has a low latency compared with other multiprocessor architectures which can support the same number of processors. The cache coherence is maintained easily on each bus. This architecture is a shared memory multiprocessor system, and is modular and scalable

Keywords

computer interfaces; parallel architectures; cache coherence; isolated buses; low latency; multiple bus architecture; orthogonal bus structure; scalable orthogonal multiprocessor architecture; shared memory; Computer architecture; Computer science; Concurrent computing; Large-scale systems; Memory architecture; Message passing; Multiprocessing systems; Parallel architectures; Switches; System buses;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-2470-1

Type

conf

DOI

10.1109/ACSSC.1991.186414

Filename

186414