Annealing of heavy-ion induced floating gate errors: LET and feature size dependence

Author

Bagatin, Marta ; Gerardin, Simone ; Cellere, Giorgio ; Paccagnella, Alessandro ; Visconti, Angelo ; Beltrami, Silvia ; Bonanomi, Mauro ; Harboe-Sørensen, Reno

Author_Institution

Dipt. di Ing. dell´´Inf., Univ. di Padova, Padova, Italy

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

112

Lastpage

118

Abstract

We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of rough bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes.

Keywords

NAND circuits; NOR circuits; annealing; flash memories; LET; NAND architecture; NOR architecture; cell feature size; cell threshold voltage distribution; feature size dependence; flash memories; heavy-ion induced floating gate errors; heavy-ion irradiation; heavy-ion strikes; multilevel cells; room temperature annealing; rough bit errors evolution; statistical property; Annealing; Charge carrier processes; Computer architecture; Ions; Microprocessors; Radiation effects; Temperature measurement; Annealing; Flash memories; Heavy ions; Radiation Effects;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on

Conference_Location

Bruges

ISSN

0379-6566

Print_ISBN

978-1-4577-0492-5

Electronic_ISBN

0379-6566

Type

conf

DOI

10.1109/RADECS.2009.5994564

Filename

5994564