Physical evidence for the electrical signature of SEGR on thin vertical oxides

Analysis techniques have been done to provide the physical evidence that the electrical signature observed from a single event gate rupture (SEGR) event on a deep trench oxide capacitor from 90 nm bulk complementary metal oxide semiconductor (CMOS) technology, used for the reduction of single event upsets (SEU), does identify that dielectric breakdown has occurred. SEGR damaged trench oxides were identified via a voltage contrast technique using a focused ion beam (FIB). The FIB was used to delayered and expose the deep trenches. A wet chemical etch was used to identify the location of SEGR leakage path. The oxide rupture location was observed at the top of the deep trench capacitor.