Pipelining saturated accumulation

Author

Papadantonakis, Karl ; Kapre, Nachiket ; Chan, Stephanie ; DeHon, Andre

Author_Institution

Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA

fYear

2005

fDate

11-14 Dec. 2005

Firstpage

19

Lastpage

26

Abstract

Aggressive pipelining allows FPGAs to achieve high throughput on many digital signal processing applications. However, cyclic data dependencies in the computation can limit pipelining and reduce the efficiency and speed of an FPGA implementation. Saturated accumulation is an important example where such a cycle limits the throughput of signal processing applications. We show how to reformulate saturated addition as an associative operation so that we can use a parallel prefix calculation to perform saturated accumulation at any data rate supported by the device. This allows us, for example, to design a 16-bit saturated accumulator which can operate at 280MHz on a Xilinx Spartan-3 (XC3S-5000-4), the maximum frequency supported by the component´s DCM

Keywords

field programmable gate arrays; logic design; pipeline arithmetic; FPGA implementation; associative operation; cyclic data dependency; digital signal processing application; field programmable gate array; parallel prefix calculation; pipelining; saturated accumulation; saturated addition; Application software; Computer science; Delay; Digital signal processing; Field programmable gate arrays; Frequency; Pipeline processing; Signal processing; Table lookup; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on

Conference_Location

Singapore

Print_ISBN

0-7803-9407-0

Type

conf

DOI

10.1109/FPT.2005.1568519

Filename

1568519