Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique

Two modified triple modular redundancy (TMR) structures based on asynchronous circuit technique are proposed in this paper. Double modular redundancy (DMR) structure uses asynchronous C element to output and keep the correct value of two redundant storage cells. Temporal spatial triple modular redundancy structure with DCTREG (TSTMR-D) uses explicit separated master and slave latch structure of de-synchronous pipeline. Three soft error tolerant 8051 cores with DMR, TMR and TSTMR-D respectively are implemented in SMIC 0.35mum process. Fault injection experiments are also included. The experiment results indicate that DMR structure has a relatively low overhead on both area and latency than TMR, while tolerances SEUs in sequential logic. TSTMR-D structures can tolerance soft errors in both sequential logic and combinational logic with reasonable area and latency overhead