An Approach to Minimizing Functional Constraints

Functional constraints are an integral part of the VLSI design methodology. Pseudo-functional scan ATPG and untestable fault identification are two areas in test where functional constraints are widely used. The number and complexity of these constraints for large designs become a limiting factor in their successful usage. In this paper the authors define a constraint minimization problem and present a powerful framework to simplify such constraints. The feasibility and effectiveness of this approach is demonstrated by using untestability analysis of large industrial benchmarks as a case study