A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process

Author

Doi, Yoshiyasu ; Masaki, Syunitirou ; Chiba, Takaya ; Higashi, Hirohito ; Yamaguchi, Hisakatsu ; Takauchi, Hideki ; Ishida, Hideki ; Gotoh, Kohtaroh ; Ogawa, Junji ; Tamura, Hirotaka

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

131

Lastpage

134

Abstract

We describe a 16-channel 2.5Gb/s high-speed transceiver that operates off a single supply voltage ranging from 0.8V to 1.3V. We fabricated the transceiver in a 90nm standard CMOS, using CMOS full-swing circuits except for a limited number of speed- and timing-critical circuits that were implemented in reduced-swing circuit topologies. The reduced-swing circuits were the last-stage 2:1 selector of the multiplexer, transmitter output stage, the decision latches, phase interpolators and delay cells in the VCOs. At a supply voltage of 0.8V, the power consumption of 16-channel transceiver is 362mW, i.e., 23mW per transceiver channel.

Keywords

CMOS digital integrated circuits; flip-flops; multiplexing equipment; transceivers; voltage-controlled oscillators; 0.8 to 1.3 V; 2.5 Gbit/s; 362 mW; 90 nm; CMOS full-swing circuits; CMOS process; decision latches; delay cells; high-speed serial transceiver; multiplexer; phase interpolators; reduced-swing circuits; speed-critical circuits; timing-critical circuits; transmitter output stage; voltage controlled oscillator; CMOS process; CMOS technology; Circuit topology; Clocks; Equalizers; Frequency synchronization; Latches; Multiplexing; Transceivers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568625

Filename

1568625