Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations

On-chip inductance impact on signal integrity, complicated by process variations, becomes challenging for global interconnects in nanometer designs. Simulation and analysis of on-chip buses are presented for the impact of inductance in the presence of process variations. Results show that in 90nm technology there is significant inductive impact on max-timing (∼9% push-out vs. RC delay) and noise (∼2× RC noise). Device and interconnect variations add ∼4% into RLC max-timing impact, while their impact on RLC signal noise is nonappreciable.