Simulation and Analysis of Fully Depleted Strained-Si SOI MOSFET

Author

Jing, Liu ; Yong, Gao ; Yuan-Yuan, Huang

Author_Institution

Xi´´an Univ. of Technol., Xi´´an

fYear

2007

fDate

26-28 Sept. 2007

Firstpage

143

Lastpage

145

Abstract

A systematic study on the fully depleted strained-Si SOI MOSFET has been demonstrated in this paper. The strained-Si n-FET and p-FET both show significant drain current enhancement of 21% and 14.3%, and peak-Gm enhancement of 16.3% and 10%, respectively. The enhancement in n-FET is larger than that in p-FET due to more significant mobility enhancement for electron than for hole. Moreover, the relationship between threshold-voltage and Ge content is also examined. It is confirmed that threshold-voltage decreases with increasing of Ge content. Therefore, there must be a trade off in Ge content depending on device electrical characteristics.

Keywords

MOSFET; silicon; silicon-on-insulator; Si; drain current enhancement; strained-Si SOI MOSFET; threshold-voltage; Analytical models; Charge carrier processes; Electric variables; Electron mobility; Etching; Germanium silicon alloys; MOSFET circuits; Parasitic capacitance; Silicon germanium; Silicon on insulator technology; fully depleted; peak-Gm; strained-Si; tensile strain; threshold-voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, 2007. ISIC '07. International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-4244-0797-2

Electronic_ISBN

978-1-4244-0797-2

Type

conf

DOI

10.1109/ISICIR.2007.4441817

Filename

4441817