DocumentCode
2909003
Title
A high throughput divider implementation
Author
Guo, Xinyu ; Sechen, Carl
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
2005
fDate
18-21 Sept. 2005
Firstpage
507
Lastpage
510
Abstract
Intensive arithmetic computations in 3D graphic applications and scientific computations demand parallel division. A high throughput divider implemented in output prediction logic (OPL) is presented. By combining the carry-free nature of a redundant number system and the high-speed characteristics of OPL, the performance of the dividing unit is tremendously improved. Fabricated in 0.18μm/1.8V CMOS, the radix-4 divider is capable of achieving an operating frequency of 1.2GHz.
Keywords
CMOS logic circuits; UHF integrated circuits; dividing circuits; high-speed integrated circuits; redundant number systems; 0.18 micron; 1.2 GHz; 1.8 V; CMOS process; high throughput divider; high-speed characteristics; output prediction logic; parallel division; radix-4 divider; redundant number system; Adders; Arithmetic; CMOS logic circuits; Computer applications; Concurrent computing; Delay; Frequency conversion; Graphics; Iterative algorithms; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN
0-7803-9023-7
Type
conf
DOI
10.1109/CICC.2005.1568717
Filename
1568717
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