A 0.18 μm CMOS on-chip skin detection scheme based on NPNP-triple-junction structure

Author

Xiaojin Zhao ; Chen, Shoushun ; Boussaid, Farid ; Bermak, Amine

Author_Institution

Western Australia Univ., Kowloon

fYear

2007

fDate

26-28 Sept. 2007

Firstpage

333

Lastpage

336

Abstract

In this paper, a 0.18 μm CMOS color processing scheme based on NPNP-triple-junction structure is proposed to achieve real-time skin detection. The need for building complex demosaicing circuitry is completely eliminated, which dramatically reduces the fabrication cost and simplifies the pixel space sampling algorithm. In addition, real-time detection is enabled through the use of logarithmic readout mode and Gilbert normalization cell. The fabricated chip and related measurement results have verified the concept of a compact, low cost, CMOS fully compatible micro-sensor suitable for skin detection.

Keywords

CMOS integrated circuits; image colour analysis; object detection; system-on-chip; CMOS color processing; CMOS on-chip skin detection; Gilbert normalization cell; NPNP-triple-junction structure; VLSI; demosaicing circuitry; logarithmic readout mode; pixel space sampling; real-time skin detection; size 0.18 μm; CMOS process; CMOS technology; Circuits; Color; Costs; Face detection; Layout; Object detection; Skin; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits, 2007. ISIC '07. International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-4244-0796-5

Electronic_ISBN

978-1-4244-0797-2

Type

conf

DOI

10.1109/ISICIR.2007.4441866

Filename

4441866