DocumentCode
2909550
Title
A 40-MHz CMOS RSSI with Data Slicer
Author
The, Yen Ju ; Choi, Yeung Bun ; Yeoh, Wooi Gan
Author_Institution
Inst. of Microelectron., Singapore
fYear
2007
fDate
26-28 Sept. 2007
Firstpage
345
Lastpage
348
Abstract
This paper presents an integrated 40 MHz CMOS RSSI with data slicer. The RSSI circuit uses 6 stages of limiting amplifier with feedback type dc-offset cancellation. The data slicer adopts a rail-to-rail comparator to get the binary data. Implemented in 0.13 mum CMOS technology, the designed RSSI achieves linearity of -48 to 8 dBm with plusmn1 dB error and consumes 3.6 mA total current for 2.5 V supply.
Keywords
CMOS integrated circuits; VHF circuits; comparators (circuits); integrated circuit design; limiters; CMOS RSSI; CMOS technology; current 3.6 mA; data slicer; feedback type dc-offset cancellation; frequency 40 MHz; limiting amplifier; rail-to-rail comparator; received signal strength indication; size 0.13 mum; voltage 2.5 V; Amplitude shift keying; Bandwidth; CMOS technology; Circuits; Frequency; Gallium nitride; Limiting; Linearity; Monitoring; Signal processing; RSSI; data slicer; limiting amplifier; rail-to-rail comparator;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location
Singapore
Print_ISBN
978-1-4244-0797-2
Electronic_ISBN
978-1-4244-0797-2
Type
conf
DOI
10.1109/ISICIR.2007.4441869
Filename
4441869
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