• DocumentCode
    2910062
  • Title

    Design of a 4-valued digital multiplier using an artificial heterogeneous two-layered neural network

  • Author

    Hu, Chia-lun J.

  • Author_Institution
    Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA
  • fYear
    1992
  • fDate
    27-29 May 1992
  • Firstpage
    84
  • Lastpage
    87
  • Abstract
    A two-layered parallel cascaded neural network using heterogeneous binary and ternary artificial neurons is used to implement the four-valued digital multiplication process. The hardware design is derived from a general M-valued perceptron mapping theory. It requires only three binary neurons and one ternary neuron. The use of heterogeneous perceptron mapping techniques allows the design to be reasonably simple and accurate
  • Keywords
    artificial intelligence; many-valued logics; multiplying circuits; neural nets; 4-valued digital multiplier; M-valued perceptron mapping theory; artificial heterogeneous two-layered neural network; digital multiplication process; hardware design; parallel cascaded neural network; Adders; Artificial neural networks; Circuits; Digital systems; Hardware; Iron; Neural networks; Neurons; Process design; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on
  • Conference_Location
    Sendai
  • Print_ISBN
    0-8186-2680-1
  • Type

    conf

  • DOI
    10.1109/ISMVL.1992.186781
  • Filename
    186781