An R-2R Ladder-Based Architecture for High Linearity DACs

Digital to analog conversion performance is mainly characterized by its resolution, linearity and speed. Additional implementation characteristics include area and power dissipation. This paper presents a DAC architecture based on the conventional R-2R ladder topology that is able to derive a high-resolution, high-linearity and high-speed DAC, while requiring reasonable operating power and implementation area in a standard CMOS technology. Simulation results, derived both from numerical and circuit-level simulations, point out that the proposed architecture is able to derive any desirable resolution and linearity, without requiring low mismatch technologies or expensive trimming procedures.