Application of Genetic Algorithms for Run-Time Reconfiguration Using Flexible Bus-Macros

Author

Nahas, Carlos ; Groza, Voicu

Author_Institution

Univ. of Ottawa, Ottawa

fYear

2007

fDate

1-3 May 2007

Firstpage

1

Lastpage

5

Abstract

This paper presents updated results for experiments published in a previous conference, namely RoEduNet 2006. The purpose is to present a method of performing the task of dynamic temporal placement for run-time reconfiguration (RTR), which requires that hardware resources be allocated for specific timeslots on an FPGA. The work presents the use of genetic algorithms as the method to place pre-wired logic circuits onto the FPGA, in order to produce a non-deterministic solution for an acceptable placement. In addition, this paper will discuss the elimination of unusable placements.

Keywords

field programmable gate arrays; genetic algorithms; resource allocation; FPGA; RoEduNet 2006; flexible bus-macros; genetic algorithms; prewired logic circuits; resources allocation; run-time reconfiguration; Built-in self-test; Circuit testing; Field programmable gate arrays; Genetic algorithms; Information technology; Instrumentation and measurement; Logic devices; Logic testing; Mathematical model; Runtime; Application of Genetic Algorithms; Run-Time Reconfiguration;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference Proceedings, 2007. IMTC 2007. IEEE

Conference_Location

Warsaw

ISSN

1091-5281

Print_ISBN

1-4244-0588-2

Type

conf

DOI

10.1109/IMTC.2007.378986

Filename

4258321