Space Compaction for Embedded Cores-Based System-on-Chips (SOCs) Using Fault Graded Output Merger

The design of space-efficient support hardware for built-in self-testing (BIST) is of crucial importance in the design and manufacture of complex system-on-chip (SOC) circuits. This paper reports on a new space compression technique that facilitates designing such circuits using pseudorandom and compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The compaction technique utilizes the concept of fault grading of output lines based on strong and weak compatibility information of output pairs. The proposed technique guarantees simple design with 100% fault coverage for single stuck-line faults, low CPU simulation time, and acceptable area overhead. Simulation runs on ISCAS 85 combinational benchmark circuits with FSIM and ATALANTA programs confirm the usefulness of the suggested approach.