DocumentCode

2916536

Title

A Verification Guide for the Perplexed Designer: Matching Verification Techniques and Design Tasks

Author

Subrahmanyam, P.A.

Author_Institution

AT&T Bell Laboratories

fYear

1992

fDate

4-7 Jan 1992

Firstpage

341

Lastpage

342

Keywords

Automata; Boolean functions; Circuit simulation; Circuit synthesis; Design automation; Hardware design languages; Humans; Logic; Safety;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1992. Proceedings., The Fifth International Conference on

ISSN

1063-9667

Print_ISBN

0-8186-2465-5

Type

conf

DOI

10.1109/ICVD.1992.658080

Filename

658080