• DocumentCode
    2916887
  • Title

    Preliminary study of custom computing hardware for the 3x+1 problem

  • Author

    Ichikawa, Shuichi ; Kobayashi, Naohiro

  • Author_Institution
    Dept. of Knowledge-Based Inf. Eng., Toyohashi Univ. of Technol., Japan
  • Volume
    D
  • fYear
    2004
  • fDate
    21-24 Nov. 2004
  • Firstpage
    387
  • Abstract
    The 3x+1 problem is a simple but unsolved problem in number theory. Though computational verifications have been attempted for this problem, they are very time-consuming. This study describes the custom hardware designs for the 3x +1 problem, and discusses the feasibility of acceleration. A prototype hardware was implemented and evaluated with an Altera FPGA.
  • Keywords
    field programmable gate arrays; number theory; 3x+1 problem; Altera FPGA; custom computing hardware; field programmable gate array; number theory; prototype hardware; Hardware;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2004. 2004 IEEE Region 10 Conference
  • Print_ISBN
    0-7803-8560-8
  • Type

    conf

  • DOI
    10.1109/TENCON.2004.1414951
  • Filename
    1414951
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2916887