A RISC controlled motion estimation processor for MPEG-2 and HDTV encoding

Author

Charlot, D. ; Bard, J.-M. ; Canfield, B. ; Cuney, C. ; Graf, A. ; Pirson, A. ; Teichner, D. ; Yassa, F.

Author_Institution

Thomson Consumer Electron. Components, Meylan, France

Volume

5

fYear

1995

fDate

9-12 May 1995

Firstpage

3287

Abstract

Describes the architecture of a hierarchical motion estimation processor, with respect to the MPEG-2 encoding standard. This processor can also be used in HDTV applications. The motion estimation processing is in 2 steps: first full-pixel then half-pixel. Several modes are possible, depending on the image types (I, P or B-MPEG terminology, frame based or field based). A decision is taken in this processor to choose the best mode. The architecture is based on a RISC controller, external DRAMs to store anchor frames and specific hardware for processing the distortions. The architecture was chosen to achieve high performance, programmability and high memory bandwidth

Keywords

VLSI; digital signal processing chips; digital television; high definition television; motion estimation; programmable controllers; reduced instruction set computing; telecommunication control; television interference; television standards; video coding; B-MPEG terminology; HDTV encoding; I-MPEG terminology; MPEG-2 encoding; P-MPEG terminology; RISC controlled motion estimation processor; anchor frames; architecture; distortions; external DRAMs; field based terminology; frame based terminology; image types; memory bandwidth; performance; programmability; Consumer electronics; Digital TV; Encoding; HDTV; Motion control; Motion estimation; Process control; Random access memory; Reduced instruction set computing; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on

Conference_Location

Detroit, MI

ISSN

1520-6149

Print_ISBN

0-7803-2431-5

Type

conf

DOI

10.1109/ICASSP.1995.479588

Filename

479588