MTSCStack: An effective technique to decrease leakage power in VLSI circuits

The demands of future computing have led to challenges of very deep submicron (DSM) regime. As a result, leakage power dissipation is rapidly becoming a substantial contributor to the total power dissipation as threshold voltage becomes small, according to the International Technology Roadmap for Semiconductors (ITRS). In this paper a new low leakage power technique, named “MTSCStack” has been proposed. The proposed method is based on reducing leakage power in active mode and standby mode while saving exact logic state during sleep mode. Library designed using 65 nm BSIM 4 model of Berkeley Predictive Technology Model (BPTM) has been used to simulate proposed technique.