DocumentCode
2919542
Title
Electronic circuit analogue model for CMOS devices
Author
Varga, L.
Author_Institution
Defence Res. Establ. Ottawa, Ont., Canada
fYear
2001
fDate
10-14 Sept. 2001
Firstpage
266
Lastpage
268
Abstract
A 2-D electronic analogue simulator circuit is introduced to model the latch-up vulnerability in CMOS circuits. The simulator is applied to analyze the relative radiation hardness as a function of circuit layout and distribution of substrate contacts. The results of simulations show good agreement with elsewhere obtained experimental flash X-ray results on similar structures.
Keywords
CMOS integrated circuits; finite element analysis; integrated circuit layout; integrated circuit modelling; radiation hardening (electronics); 2-D electronic analogue simulator circuit; CMOS devices; circuit layout; electronic circuit analogue model; finite element analysis; latch-up vulnerability; radiation hardness; substrate contact distribution; CMOS analog integrated circuits; Circuit simulation; Circuit testing; Electronic circuits; Inverters; Resistors; Semiconductor device modeling; Semiconductor diodes; Substrates; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Radiation and Its Effects on Components and Systems, 2001. 6th European Conference on
Print_ISBN
0-7803-7313-8
Type
conf
DOI
10.1109/RADECS.2001.1159291
Filename
1159291
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