Enabling Effective Yield Learning through Actual DFM-Closure at the SoC Level

The aim of this paper is to extend the intensive yield learning and manufacturability process further into the process life cycle. This necessarily means employing chips of high circuit complexity, up to the final products complexity. In this way, the actual effects that the design flow will have in combining low-levels of IP can be understood more accurately. The paper will also describe how analysis recipes can be used to isolate different behavior effects and associate them to failure cause. We will also demonstrate techniques which can be adopted in the early ramp-up phase to improve the DFM rules maturity level by progressively fine tuning them with respect to the measured data.