DocumentCode
2925570
Title
Multi-core aware process mapping and its impact on communication overhead of parallel applications
Author
Rodrigues, Eduardo R. ; Madruga, Felipe L. ; Navaux, Philippe O A ; Panetta, Jairo
Author_Institution
Inst. of Inf., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
fYear
2009
fDate
5-8 July 2009
Firstpage
811
Lastpage
817
Abstract
We propose an approach to reduce the execution time of applications with a steady communication pattern on clusters of multi-core processors by leveraging the asymmetry of core communication speeds. In addition to the well known fact that communication link speeds on a fixed cluster vary with processor selection, we consider one effect of multicore processor chips: link speeds vary with core selection within a single processor chip. The approach requires measuring link speeds among cluster cores as well as communication volumes and computational loads of the selected application processes. This data is fed into the dual recursive bipartitioning method to obtain close to optimal application process placement on cluster cores. We apply this approach to a real world application achieving sensible execution time reduction without even recompiling source code.
Keywords
microprocessor chips; communication link speeds; communication overhead; dual recursive bipartitioning method; execution time reduction; multicore aware process mapping; multicore processor chips; parallel applications; single processor chip; Application software; Costs; Informatics; Multicore processing; Predictive models; Production; Semiconductor device measurement; Velocity measurement; Volume measurement; Weather forecasting;
fLanguage
English
Publisher
ieee
Conference_Titel
Computers and Communications, 2009. ISCC 2009. IEEE Symposium on
Conference_Location
Sousse
ISSN
1530-1346
Print_ISBN
978-1-4244-4672-8
Electronic_ISBN
1530-1346
Type
conf
DOI
10.1109/ISCC.2009.5202271
Filename
5202271
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