CAD challenges for 3D ICs

A fundamental shift in the technology has occurred at 90 nm CMOS and beyond where the interconnect resistance has been increasing so much that the distance a clock cycle can reach has been dwindling as a fraction of the dimension of the chip. to cause a repeater explosion problem. This problem translates into an explosion of repeaters which not only added significant overhead in area but also power, as repeaters are major contributors to leakage. By reaching out to the vertical dimension, 3D technology has the potential of easing repeater explosion (Figure 1), reducing latency between units, increasing memory bandwidth and integrating heterogeneous technologies. However, in order to exploit the full potential of 3D technology, new challenges in the area of system level design and analysis, physical design, thermal analysis need to be addressed.