• DocumentCode
    2926416
  • Title

    FastRoute 4.0: Global router with efficient via minimization

  • Author

    Xu, Yue ; Zhang, Yanheng ; Chu, Chris

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA
  • fYear
    2009
  • fDate
    19-22 Jan. 2009
  • Firstpage
    576
  • Lastpage
    581
  • Abstract
    The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by charging a cost for vias in the maze routing cost function. In this paper, we present a global router that addresses the via number optimization problem throughout the entire global routing flow. We introduce the via aware Steiner tree generation, 3-bend routing and layer assignment with careful ordering to reduce via count. We integrate these three techniques into FastRoute 3.0 and achieve significant reduction in both via count and runtime.
  • Keywords
    VLSI; circuit CAD; integrated circuit design; network routing; 3-bend routing; FastRoute 4.0; Steiner tree generation; VLSI designs; global router; global routing stage; layer assignment; maze routing cost function; number optimization; Cost function; Design for manufacture; Dynamic programming; Integrated circuit interconnections; Minimization; Power generation; Routing; Runtime; Timing; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
  • Conference_Location
    Yokohama
  • Print_ISBN
    978-1-4244-2748-2
  • Electronic_ISBN
    978-1-4244-2749-9
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2009.4796542
  • Filename
    4796542