A hardware efficient parallel Viterbi algorithm

Author

Black, Peter ; Meng, T.H.-Y.

Author_Institution

Inf. Syst. Lab., Stanford Univ., CA, USA

fYear

1990

fDate

3-6 Apr 1990

Firstpage

893

Abstract

A hardware efficient block processing scheme is proposed for concurrent implementation of the Viterbi algorithm. The throughput increase is proportional to the increase in hardware complexity at the expense of latency. Advantages of the algorithm over other parallel schemes are that the reduction of the information rate due to bit stuffing at the transmitter and extraction of block synchronization from the received data are not necessary. The scheme is well suited to the problem of sequence estimation in the presence of intersymbol interference, although it can be applied to any decoder based on the Viterbi algorithm

Keywords

computerised signal processing; decoding; parallel algorithms; parallel architectures; state estimation; ISI; concurrent implementation; decoder; hardware complexity; hardware efficient block processing scheme; intersymbol interference; parallel Viterbi algorithm; sequence estimation; throughput increase; CMOS technology; Concurrent computing; Data mining; Decoding; Delay; Hardware; Information rates; Intersymbol interference; Iterative decoding; Markov processes; Sequences; State estimation; Throughput; Transmitters; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.115987

Filename

115987