Physical and electrical analysis of the stress memorization technique (SMT) using poly-gates and its optimization for beyond 45-nm high-performance applications

We have investigated the stress memorization technique (SMT) using poly-gates through both physical analysis and electrical characterization. It has been clarified that channel compressive strain in the vertical direction originates from poly-gate volume expansion, which is associated with both grain growth and highly concentrated impurities implanted into gates. By optimizing key factors in the SMT process with arsenic (As) source/drain (SD), we have achieved competitive NFET drive current compared to that with phosphorus (P) SD with lower parasitic resistance which requires extra offset spacers for SD implantation. For further scaling of gate pitches beyond 45-nm node and enhancing NFET performance, well-optimized SMT with As-NSD is indispensable technology for both poly and metal gates.