A new strategy for test pattern generation in sequential circuits

This paper presents a new strategy for automatic test pattern generation for synchronous sequential circuits. It is known that it is difficult and time-consuming to detect stuck-at faults in sequential circuits. A sequence of test patterns is often required to detect a target fault in sequential circuits using conventional sequential test pattern generators. In order to reduce CPU time and the number of test patterns and to improve fault coverage, we propose a new strategy for sequential test pattern generation using the clock isolation, which can enhance the performance of the conventional test pattern generator. Furthermore the test pattern can be generated efficiently using a new testability measure, a sixteen-valued logic, complete multiple-path sensitisation and a modified algorithm of conventional sequential test pattern generation