Output-column folding for cellular-architecture FPGAs

The work described in this paper is a component of our comprehensive approach to the low-level synthesis (logic synthesis and layout synthesis) of Cellular-Architecture (CA-type) FPGAs. A multiple-output logic function is represented as a collection of complex terms. Each term is assigned to a separate row of a CA-type FPGA. These terms are collected using EXOR or OR gates to create function outputs, initially one output per column. In this paper an algorithm for multiple column folding of CA-type FPGAs is presented. The formulation of the problem is similar to the gate matrix layout problem but with additional constraints. Experimental results are very encouraging