Using binary decision diagrams to speed up the test pattern generation of behavioral circuit descriptions written in hardware description languages

In this paper, we focus on test pattern generation for circuit descriptions written in hardware description languages according to the circuit behavior. We develop an algorithmic improvement method which is devoted to speed up the deterministic and fault-oriented test systems which deal with such circuit descriptions. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach