Hierarchical statistical verification of large full custom CMOS circuits

Author

van der Wal, A.B. ; Arendsen, R.G.J. ; Herrmann, O.E. ; Brombacher, A.C.

Author_Institution

Dept. of Electr. Eng., Twente Univ., Enschede, Netherlands

Volume

1

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

443

Abstract

This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient

Keywords

CMOS digital integrated circuits; application specific integrated circuits; circuit CAD; circuit analysis computing; integrated circuit design; integrated circuit modelling; statistical analysis; behavioural models; design verification process; digital CMOS circuits; hierarchical statistical verification; large full custom CMOS circuits; statistical process variation; Application specific integrated circuits; Buildings; Circuit simulation; Design methodology; Semiconductor device modeling; Silicon; Switches; Switching circuits; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.408834

Filename

408834