Session 18: Characterization, reliability, and yield - Strain optimization and performance

In this session the first paper proposes a new strain mapping technique with sub-nano meter spatial resolutions using TEM. The strain maps obtained by this technique have been shown to contribute to the understanding of mobility enhancement mechanism in nano-scale MOSFETs. The second paper, which is an invited paper from UMC, provides guidelines for developing high-end strained CMOS technologies with acceptable reliability for 65 nm node and beyond. The third paper in this session shows results of IC timing and delay optimization by backside FIB processing and a comparison of the same with conventional and strained technologies. The next paper deals with defect reduction by proper plasma process optimization in order to achieve high mobility and performance improvements. The final paper in the session then addresses the variability issues in circuits by providing an understanding of high drain bias effects on threshold voltage fluctuations by an optimization of halo and drain-induced-barrier-lowering.