Trimming of IC timing and delay by backside FIB processing - comparison of conventional and strained technologies

Rapid prototyping options provided by backside FIB preparation are expanded by trimming device delay to the desired quantity. Using inverter chains in 180 nm standard CMOS technology, proper FIB backside treatment is demonstrated to speed up or slow down devices by more than 20%. This result agrees well with device simulations and applies in principle to any technology. Devices from a 65 nm strained CMOS process show an even increased effect, further expanding the trimming potential of backside FIB.