Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise

Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. For so-called strong PUFs, the number of challenge-response pairs (CRPs) increases exponentially with the required chip area in the ideal case. They can provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. Modeling of the CRP behavior through Machine Learning (ML) has shown to be a threat however. In this paper, we exploit repeatability imperfections of PUF responses as a side channel for model building. We demonstrate that 65nm CMOS arbiter PUFs can be modeled successfully, without utilizing any ML algorithm. Data originates from real-world measurements and hence not from simulations. Modeling accuracies exceeding 97% are obtained, which is comparable with previously published ML results. Information leakage through the exploited side channel should be considered for all strong PUF designs. Combined attack strategies, whereby repeatability measurements facilitate ML, might be effective and are recommended for further research.