Session 24: Special Evening Session highlights of ISSCC 2008

In this Special Evening Session four outstanding papers published at the 2008 International Solid-State Circuit Conference (ISSCC) are presented to the IEDM audience. All papers are focused on the idea that circuit-technology interaction plays an important role for numerous applications, and that related circuit designs gain benefit from thorough technology understanding and vice versa. In the first paper by Fatih Hamzaoglu et al., from Intel, utilizing a 45nm high-k metal-gate CMOS technology, special emphasis is put on design-based solutions to deal with stability and leakage issues of a 153Mb SRAM with 0.346μm² cell area. Careful body biasing and implementation of sleep transistor techniques enable achievement of these goals. Whereas the first paper focuses on mainstream logic applications, the second paper by Joachim Burghartz et al., from IMS CHIPS, discusses CMOS imager chips for in-vivo biomedical purposes. A sub-retinal CMOS imager implant is shown to restore vision of patients suffering from retinitis pigmentosa. Additionally, an endoscopy camera chip using an amorphous α-Si layer above standard CMOS is demonstrated. The last two papers highlight novel approaches for non-volatile memories. Ki-Tae Park et al., from Samsung, Korea, describe a multi-level 4Gb NAND Flash device in 45nm technology. High area efficiency is achieved by using two stacked Si layers providing 2Gb each. Architecture and operation issues are discussed with respect to cell properties in this 3D arrangement. The last paper by Ferdinando Bedeschi et al., from Numonyx, considers a phase-change memory approach combining the properties of non-volatility and fast read and write access. A 256Mb multi-level test-chip is presented based on a 90nm microtrench technology and using Ge2Sb2Te5 as the phase-change material.